The present invention relates to computer processing systems, and more specifically, to caching of perceptron branch patterns using ternary content addressable memory.
An instruction pipeline in a computer processor improves instruction execution throughput by processing instructions using a number of pipeline stages, where multiple stages can act on different instructions of an instruction stream in parallel. A conditional branch instruction in an instruction stream may result in a pipeline stall if the processor waits until the conditional branch instruction is resolved in an execution stage in the pipeline before fetching the next instruction in an instruction fetching stage for the pipeline. A branch predictor may attempt to guess whether a conditional branch will be taken or not. Rather than stall when a branch is encountered, a pipelined processor uses branch prediction to speculatively fetch and execute instructions along the predicted path. Branch prediction is used to assist in the flow of executing instructions.